WELCOME
(A) Digital/System Level Designs
1. SoC-based Processor Design for Wearable Gas Sensor Detection System
2. Design and performance analysis of multiported memories for multiple data access
3. Design and performance analysis of a reconfigurable FIFO and LIFO memories [Video] [pdf]
4. Design and performance analysis of burst memory write and read
(B) Biomedical Applications:
1. Design and development of non-invasive an early detection system for
neonatal Jaundice in Newborn babies
2.A study of DNA fingerprinting for early cancer detection (collaborator: AMDI, USM Penang)
3. A study of a double buffering-based efficient loader for protein sequence alignment.
4. Design and Development of a Generic Loader and Storage Elements for Protein Sequencer
5. DNA Chip Design for Early Stage Cancer Diagnosis
6. DNA Microarray Data Clustering using FPGA
7. Systolic array-based Multiplier Design for Biomedical Applications
8. High Performance Logarithmic Multiplier Design
9. High Performance DNA Sequencer for HIV Detection
10. High Performance Protein Sequencer for Premature Stage Cancer Detection
11. Abnormalities Heart Beat Detection:
Selected Publications
1. M. N. Isa, K. Benkrid, and T. Clayton, "Efficient architecture and scheduling technique for pairwise sequence alignment," ACM SIGARCH Comput. Archit. News, vol. 40, pp. 26-31, 2012.[pdf]
2. M. N. Isa, K. Benkrid and T. Clayton “A Highly Efficient Substitution Matrix Loader for Pairwise Sequence Alignment” presented at The 24th International Conference on Microelectronics (ICM), 17-20 December 2012, Algeria, pp. 1-4.[pdf]
3. M. N. Isa, K. Benkrid, T. Clayton, C. Ling, and A. T. Erdogan "An FPGA-based parameterised and scalable optimal solutions for pairwise biological sequence analysis," presented at 2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 6-9 June 2011, San Diego, California,US. pp. 344-351. [pdf]
4. M. N. Isa, K. Benkrid and T. Clayton “A Novel Efficient FPGA Architecture for HMMER Acceleration" presented at 2012 International Conference on ReConFigurable Computing and FPGAs (ReConFig), 5-7 December 2012, Cancun, Mexico. pp. 1-6.[pdf]
5. C. Hong, K. Benkrid, M. N. Isa and X.Iturbe “Run-time Reconfigurable System for Adaptive High Performance Computing” The Fourth International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2013, 13-14 June 2013, Edinburgh,Scotland. [pdf]
6. Isa, Mohammad Nazrin., High performance reconfigurable architectures for biological sequence alignment. PhD Thesis,University of Edinburgh, 2013. [pdf]
(C) Signal/image processing-based applications.
1. High Performance Systolic Array-based Matrix Multiplication
2. Efficient Architecture for FIR filter coefficients for signal processing applications
3. Discrete Wavelet Transform (DWT)-based analysis in detecting loss in overhead/underground cable insulator
4. Image Processing-based Character recognition for a Smart Licensed Plate Number Recognition
5. Design of a pipelined-based Multiplier Accumulator (MAC) unit for digital signal processing applications [link]
(a) SOBEL Filter Design using Verilog HDL
(b) GABOR Filter Design using Verilog HDL
Potential postgraduate research projects are not limited to the above-mentioned area of interests. Any other FPGA,
embedded projects are also welcomed.
email to nazrin.unimap.edu.my for more details
Potential Research Projects
